1. Field of the Invention
The present invention generally relates to an electronic component test device and the method for electronic component testing, and more particularly to an Integrated Circuit (ICs) test device and the method for ICs testing, which includes a plurality of shuttles having individual pick and place module.
2. Description of the Prior Art
During the packaging process, Integrated circuit (ICs) may be damaged or packaging may not be correctly performed. The failures introduced during packaging typically cause 1 percent or more of ICs to fail. Therefore it is necessary to perform the final test, which fully inspection performed on each packaged IC prior to shipment, in order to satisfy customer's requirement.
FIG. 1 shows the vertical plan view of conventional test apparatus (handler 100). The handler 100 is a piece of equipment that “handles” the ICs and makes connections to an automatic tester (not shown) via connecting cable. The handler can be divided into two zones, the input/output zone is located in the front area of the handler and the test zone is located in the rear area of the handler. There are several input trays 104 and several output trays 105 stacking arrangement in the input/output zone of the handler. The input trays are used to store the ICs, and the output trays are used to grade the tested ICs according to Binning process, which is a process of sorting parts based on some measured performance parameter such as speed of operation or other criteria.
As shown in FIG. 1, the handling of the ICs/tested ICs is fully automated from the input trays 104 to the output trays 105 by using a fast pick and place module 108 based on XY mechanism with linear motors on magnetic suspension technology. The pick and place module 108 can take any positions of the input/output zone by slipping through x-rail 109 and y-rail 108. The pick and place module 108 picks one IC from input tray 104, putting it in the front depression 115a of the shuttle 114, then moving the shuttle 114 from the input/output zone of the handler 100 to the test zone by the way of track 116.
The other pick and place module 112 located in the test zone picks another tested IC (which had completed the final test) from test area 118 by slipping through y-rail 113 and x-rail 111, and then putting it in the rear depression 115b of the shuttle 114, picking the IC that had previously stored in the front depression 115a of the shuttle 114, putting it in the socket 119 of one test area 118, and proceeding to undergo the final test.
While the final test is undergoing, the pick and place module 108 picks the tested IC which had previously stored in the rear depression 115b of the shuttle 114 by way of the track 116, sorting it by grade then putting in the output tray 105.
Although the conventional handler 100 shown in FIG. 1 has multiple test area 118 (six in the FIG. 1), it has only one shuttle 114 and only one pick and place module 112 can pick the IC to undergo the final test. Accordingly, it is usually more than one tested IC in the test area waiting to be picked to the shuttle 114, but it can be picked until the shuttle 114 is back to the test zone from the input/output zone. In the meantime, the IC that had stored in the front depression 115a also cannot be picked into the test area, that is to say, wasting too much time on wait, and consequently tact time of conventional handler is too long, the tact time is the time needed to manufacture/test one unit of a product, measured as the elapsed time between the completion of one unit and the completion of the next. The long tact time cause the yield decreases significantly. Moreover, if the test time of the IC is shorter, then the time during wait will get longer. For example, if the time need to pick and place is 5 seconds, but the time need to complete test one IC is less than 30 seconds such as 10-15 seconds, then the time of stay in test area will become 10 seconds or longer.
The modern semiconductor production test equipment is increasingly complex to design, build and maintain. In order to decreasing the cost and increasing the yield, it is necessary to make full use of the handler 100 and to avoid idle and to increase the quantity of test per unit time, a need has arisen to propose an apparatus and a method for ICs testing, that allows for decreasing the tact time and increasing the yield.